Field of the Invention
The present invention generally relates to physical memory systems and, more specifically, to systems and methods for a fast mapping table register file allocation algorithm for single instruction multiple thread (SIMT) processors.
Description of the Related Art
State of the art graphics chips include a plurality of processing cores, where each processing core included in the plurality of processing cores executes a plurality of threads, commonly referred to as “thread groups.” Each processing core includes a register file that typically includes one-thousand and twenty-four registers that may be allocated to the thread groups. Each thread group can have a variable number of registers allocated from the register file, ranging from as few as two registers to as many as sixty-four register per thread group.
The execution order of thread groups is highly variable and often leads to allocation fragmentation within the register file. Consider a simple linear register file allocation scheme, where the register file requirements of each thread group are handled using a first-in-first-out (FIFO) technique. More specifically, a head pointer indicates the oldest allocated register while a tail pointer indicates the most-recently allocated register. If a thread group terminates early—specifically, a thread group that is associated with registers that are allocated between the head and the tail—a “hole” in the allocations of the register file is established, causing memory fragmentations within the processing core.
Accordingly, what is needed in the art is a technique for a more efficient out-of-order allocation of registers included in a register file.